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RISC-V Evolving to Address Supercomputers and AI

Read more at www.tomshardware.com

The open source RISC-V instruction set architecture is gaining more mainstream attention in the wake of Intel’s rumored $2 billion bid for SiFive, the industry’s leading RISC-V design house. Unfortunately, RISC-V has long been relegated to smaller chips and microcontrollers, limiting its appeal. However, that should change soon as RISC-V International, the organization that oversees the development of the RISC-V instruction set architecture (ISA), has announced plans to extend the architecture to high performance computing, AI, and supercomputing applications.

The RISC-V open-source ISA was first introduced in 2016, but the first cores were only suitable for microcontrollers and some basic system-on-chip designs. However, after several years of development, numerous chip developers (e.g., Alibaba) have created designs aimed at cloud data centers, AI workloads (like the Jim Keller-led Tenstorrent), and advanced storage applications (e.g., Seagate, Western Digital).

The means there’s plenty of interest from developers for high-performance RISC-V chips. But to foster adoption of the RISC-V ISA by edge, HPC, and supercomputing applications, the industry needs a more robust hardware and software ecosystem (along with compatibility with legacy applications and benchmarks). That’s where the RISC-V SIG for HPC comes into play. 

At this point, the RISC-V SIG-HPC has 141 members on its mailing list and 10 active members in research, academia, and the chip industry. The key task for the growing SIG is to propose various new HPC-specific instructions and extensions and work with other technical groups to ensure that HPC requirements are considered for the evolving ISA. As a part of this task, the SIG needs to define AI/HPC/edge requirements and plot a feature and capability path to a point when RISC-V is competitive against Arm, x86, and other architectures. 

Read more at www.tomshardware.com

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